
module top   
(  
  input [7:0] data_a, data_b,  
  input [5:0] addr_a, addr_b,  
  input wr_a, wr_b,  
  input rd_a, rd_b,  
  input clk, 
   output reg [7:0] q_a, q_b  
);  
  
reg [7:0] ram[63:0];   //declare ram  
  
//Port A  
always @ (posedge clk)  
begin  
  if (wr_a)               //write  
    begin  
     ram[addr_a] <= data_a;  
     q_a <= data_a ;  
    end  
   if (rd_a)                     
//read  
     q_a <= ram[addr_a];  
end  
  
 
//Port B  
always @ (posedge clk)  
begin  
  if (wr_b)               //write  
    begin  
     ram[addr_b] <= data_b;  
     q_b <= data_b ;  
    end  
  if (rd_b)                     
//read  
     q_b <= ram[addr_b];  
end  
  
endmodule 